nirmalsharma

Many designers are familiar with setup and hold time definitions - however, few can identify correctly the launch and capture edges and the slack/violation between two flops during timing analysis. In this post, we will cover setup/hold times in a design with clear examples.

Setup time is defined as the minimum amount of time BEFORE the clock’s active edge by which the data must be stable for it to be latched correctly. Any violation in this minimum required time causes incorrect data to be captured and is known as setup violation.

Hold time is defined as the minimum amount of time AFTER the clock’s active edge during which the data must be stable. Any violation in this required time causes incorrect data to be latched and is known as hold violation.

The setup time in a design determines the maximum frequency at which the chip can run without any timing failures. Factors affecting the setup analysis are the clock period Tclk, Clock to Q propagation delay of the launch flop Tck->q, negative clock skew Tskew, required setup time of the capture flop Tfs and combinational logic delay Tcomb between the two flops being timed. The following condition must be satisfied.

Tfs <= Tclk – Tck->q – Tskew – Tcomb

Hold analysis depends on the Tck->q, combinational logic delay, the clock skew and the hold time requirement Tfh of the capture flop. It is independent of the frequency of the clock. The condition below must be satisfied.

Tck->q + Tskew + Tcomb >= Tfh

Consider the figure below depicting a flop to flop path in the same domain with some combinational logic between them. We will now calculate the setup and hold time slacks in the design based on the given timing parameters.

Setup and Hold time illustration - Full cycle transfer

For setup checks in single cycle paths, the clock edges that are relevant is shown in the Figure above. The data required time for the capture flop B to meet setup is

Data Required time = (Clock Period + Clock Insertion Delay + Clock Skew - Setup time of the flop) = 8 + 2 + 0.25 -0.1 = 10.15 ns

The data arrival time from the launch flop is

Data Arrival time = (Clock Insertion Delay + CK->Q Delay of the launch flop + Combinational logic Delay) = 2 + 0.1 + 5 = 7.1 ns.

Setup slack is

Setup Margin = Data Required Time - Data Arrival Time = 10.15 - 7.10 = 3.05 ns

Similarly for hold checks assuming the hold time requirement of the flop B is 100 ps, the data expected time is

Data expected time = (Clock Insertion Delay + Clock skew + Hold time requirement of flop) = 2 + 0.25 +0.1 = 2.35 ns.

So the hold time slack is

Hold Margin = Data Arrival time - Data expected time = 7.10 - 2.35 = 4.85 ns

Consider the case where the clock to flop B is inverted (or that the flop is negative edge trigerred). In this particular case, the relevant edges for setup/hold are as shown in the figure below.

Setup and Hold time illustration - Half cycle transfer

In this scenario, the setup margin considering all the other parameters to be the same is

Data Required time = (half_clock_period + clock insertion delay + Ck->Q delay of flop A - Setup time required for flop B) = 4 + 2 + 0.25 -0.1 = 6.15 ns

Since the Data Arrival time remains the same, there is a setup violation of

Setup violation = 6.15 ns - 7.10 ns = -1.05 ns

There is no hold violation since the data arrival time remains the time but the data expected time is any time after (Clock skew + Hold time requirement of flop B)

Data expected time = 0.25 + 0.1 = 0.35 ns

Hold Margin = 7.10 - 0.35 = 6.75 ns

• Document in detail interface timing and signal descriptions, clock and reset strategy, modular view of the design and FSMs prior to RTL coding
• Have a comment “header” for each module with functionality description, version and a log of past changes. This can be managed using a revision control system like celarcase, CVS etc.
• Do not include more than one module in one file and the module name should match the filename in the design.
• Be generous while adding comments where necessary - like inputs and outputs.
• Indent your code and use Emacc verilog mode for connectivity to keep it error-free. Split the design into separate modules based on clock domains.
• Use separate always @ blocks for sequential and combinational logic. Always use non-blocking assignments for sequential logic and blocking assignments for combinational logic.
• Avoid “parallel_case full_case” compiler directives and always add a default clause for case statements.
• Do NOT assign the same variable in more than one always@ block.
• Use “if-else” only for priority encoders and case statements for parallel states.
• Avoid inferring latches in the design, clock gating and instantiating gates in the design to keep it technology independent.
• Register all inputs and outputs in the design to ease timing closure.
• Use dual stage synchronizer cells available in the library than two stage flops for synchronization.
• Use reset synchronizers for asynchronous resets. Add DFT bypass muxes for reset and clock controllability where necessary.
• Avoid combinational loops in the design to aid timing analysis and DFT
• Avoid using clock as data for flop inputs for hassle free DFT insertion.
• Do not mix posedge and negedge flops in the same module where possible.
• Always separate the combinational and sequential logic in a FSM with two always@ blocks.
• Always code with design reuse in mind - For example, FIFOs can be made generic and can be customized by passing parameters while being instantiated.
• Remember the thumb rule - Be conservative in what you transmit and be generous in what you receive
• Parenthesize all operations without depending on the reader to figure out the precedence of operators.